An integrated circuit may include a clamp circuit to reduce voltage stress on a protected line, for example, during an electrostatic discharge (ESD) event. The clamp circuit may include a stacked NPN bipolar transistor pair (stacked NPN) having an upper NPN bipolar transistor (upper NPN) in series with a lower NPN bipolar transistor (lower NPN), in which a collector of the upper NPN is coupled to the protected line, an emitter of the upper NPN is coupled to a collector of the lower NPN, and an emitter of the lower NPN is coupled to a ground node of the integrated circuit. Desirable characteristics of the clamp circuit may include low resistance and uniform current distribution during an ESD event, low area of the stacked NPN, and consistent breakdown voltage. The integrated circuit may include analog circuits and may include logic circuits of complementary metal oxide semiconductor (CMOS) transistors, and it may be desirable to integrate the clamp circuit in the integrated circuit without introducing additional process steps. However, in the integrated circuit configuration, it is challenging to achieve values of the resistance, current uniformity, and breakdown voltage in integrated circuits with advanced CMOS transistors.